1. Field of the Invention
The present invention relates generally to field effect transistors of the type formed in semiconductor islands supported on an insulating substrate, and more particularly to a method for doping the edges of such semiconductor islands in order to improve transistor performance.
2. Description of Related Art
Field effect transistors are generally devices formed in the surface of a semiconductor such as silicon. They consist of a pair of high conductivity regions called the "source" and the "drain" separated by a gap called the "channel." A conductor called the "gate" extends over the channel and controls the flow of current from the source to the drain when a voltage is applied across them and another voltage is applied between the source and the gate.
Field effect transistors can be either P-channel or N-channel devices. P-channel devices consist of P-type source and drain regions separated by an N-type region in which the P-channel is induced by a negative control voltage applied to the gate electrode. Conversely, an N-channel device consists of N-type source and drain regions separated by a P-type region in which an N-channel device is induced by applying a positive control voltage to the gate electrode.
An alternative to the conventional field effect transistor structure is a device which is formed in a thin layer of semiconducting material supported by an insulating substrate. Heretofore, silicon has been the semiconductor of choice and sapphire has been the preferred substrate. This technology is frequently referred to as silicon-on-sapphire, or SOS for short. Other combinations of semiconductors and insulating substrates are possible and may in fact supplant silicon-on-sapphire. In one of these the insulating substrate consists of a silicon substrate covered by a silicon dioxide layer. Since the substrate is an insulator, to the extent that it affords insulation between components formed on its silicon dioxide layer which is an insulator, this type of substrate shall be referred to herein as an insulating substrate.
In silicon-on-sapphire devices each transistor is formed in an island of silicon supported by the sapphire substrate. The gate extends across the top of the island and overlaps the edges. For sake of a convenient frame of reference, the substrate will be considered to be horizontal and the sides of the silicon islands to be vertical. In such a device each transistor is really a composite of three individual transistors, one formed by the horizontal gate portion running along the top of the silicon island, and the other two being formed by the vertical portions of the gate which run down the sides of the island, which are called "edge transistors."
One common problem found in field effect transistors with edges is the difference between the turn-on voltage of their edge transistors relative to that of their top transistor. Depending on the sign of this difference, the edge transistors can turn on at either a lower or higher voltage than the top transistor. The biggest problem occurs when the edge transistors turn on at a lower voltage, resulting in so-called "sub-threshold" conduction. This can happen if the edge transistors have a lower doping level or higher gate insulator charge density than the top transistor. Such charge density can be due to the crystallographic orientation of the edge or to charge created by radiation. Since such charge is normally positive, this problem is much more common in N-channel than in P-channel devices.
The reason for this is that both the transistor which is formed in the top of the island and the transistors which are formed on the edges of the island have a positive threshold voltage. That is, it will take a positive control voltage to establish the negative charges in the channel necessary to establish conduction between the source and drain regions for all three transistors. If the excess charge is larger in the edges than in the top surface of the silicon island, a shift in threshold caused by the excess charge will be larger in the vertically disposed transistors that it is in the horizontally disposed transistor. In the N-channel devices the effect of this threshold shift is to cause the transistor to turn on at a lower voltage than it would otherwise. The greater the threshold shift, the smaller is the voltage at which the transistor will turn on. The ultimate effect in the case of N-channel devices is that the vertically disposed transistor segments will have a lower threshold voltage than the horizontally disposed transistor segment. As a result, the composite transistor which is made up of all three segments does not have a single sharply-defined turn-on voltage. Rather, it turns on gradually, with current commencing in the vertically disposed transistors at a given voltage and this current is reinforced by the principal, horizontally disposed portion of the transistor at a slightly higher threshold voltage. The threshold shift in the N-channel devices is also undesirable because it can cause appreciable current flow in transistors which are in the "OFF" state. In an integrated circuit this can result in a large quiescent current which must be supplied by the power supply. This could be a problem, especially for battery-operated power supplies, as in a satellite.
Conversely, with P-channel devices the threshold shift caused by excess charge along the sides of the silicon island tends not to be a problem because the net effect is to increase the threshold and, hence, turn-on voltage of the vertically disposed portions of the transistor so that they require a larger voltage to conduct than does the horizontally disposed portion of the transistor. The resulting threshold increase of the composite transistor is negligible.
Excess charge can also result from the transistor being subjected to high levels of radiation. Since it is desirable that transistors remain operational while they are subjected to such levels of radiation (such transistors being referred to as "radiation hardened") as may be encountered in outer space, for example, it is highly desirable to overcome the effects of excess charge on the operation of such transistors.
Efforts have been made in the past to minimize the problem of edge conduction in silicon-on-sapphire transistors. The basic approach has been to selectively dope the edges of the silicon island so that the dopant concentration in the channels of the vertically disposed transistors would be higher than it is along the channel of the horizontally disposed transistor. This expedient has the effect of substantially cancelling the threshold shift caused by the excess charge in the edges of the silicon island. Two approaches have been used; both have been problematic. One technique is to use a process for forming silicon islands with sloped edges. This technique employs a preferential etch process using potassium hydroxide as the etchant which has the effect of leaving the silicon islands with edges having a 57.degree. slope. With the islands so formed, and leaving the island mask in place, subjecting the silicon islands to vertically impinging ions (ion implantation) would result in selectively doping the edges of the silicon islands. The problem with this technique is that, toward the base of the island where its sides meet the underlying substrate, the ions would pass right through the islands, leaving the sides in those regions undoped.
Another technique for selectively doping the edges of the silicon islands has been to leave the mask used to define the silicon islands during the etching process in place and use this mask with a subsequent step, during which a dopant is diffused into the island's edges. This edge-doping process is difficult to control insofar as both dopant density and diffusion depth are concerned.
An improved method for edge doping is the subject of my above-identified related application, Ser. No. 707,368, now abandoned. As disclosed therein, the edges of the semiconducting island in which the transistor is to be formed and which is carried upon an insulating substrate are selectively formed by a process whose initial step is to form a mask over a wafer comprising a layer of semiconducting material formed on an insulating substrate, with the mask defining the island of semiconducting material in which the transistor is to be formed. With the wafer so masked, the regions of the semiconducting material which are not covered by the mask are implanted with a dopant, while the region of the semiconducting material that is covered by the mask remains undoped. The wafer is then heated at a temperature and for a period of time selected so as to drive the dopant laterally beneath the mask by a predetermined amount. The regions of the semiconducting material not covered by the mask are then removed, typically by exposing them to an etchant which is resisted by the mask. This leaves in place the desired semiconducting island capped by the mask and doped along its edges to the preselected (lateral) depth. Thereafter the mask is removed from the top of the semiconducting island. Fabrication of the transistor may be completed through conventional steps by which the rest of the silicon island is doped, the control gate and the source and drain regions are formed, and conductors are attached to those regions.
The process just described works well. It does, however, require a measure of control, during the heating and driving step, over lateral diffusion of dopant in the semiconducting material beneath the mask, since that is what determines the lateral extent of the edge doped regions.
Accordingly, it is a principal object of the present invention to provide an alternative method for edge doping a field effect transistor of the type formed on semiconducting islands supported by an insulating substrate so as to minimize the effect of edge transistor turn-on, wherein the lateral extent of the edge doped regions is determined by other than a diffusion step.